/*
 * Register offset for DP.
 */
#define DP_LINK_BW_SET                      (0x0000 >> 2)
#define DP_LANE_COUNT_SET                   (0x0004 >> 2)
#define DP_ENHANCED_FRAME_EN                (0x0008 >> 2)
#define DP_TRAINING_PATTERN_SET             (0x000C >> 2)
#define DP_LINK_QUAL_PATTERN_SET            (0x0010 >> 2)
#define DP_SCRAMBLING_DISABLE               (0x0014 >> 2)
#define DP_DOWNSPREAD_CTRL                  (0x0018 >> 2)
#define DP_SOFTWARE_RESET                   (0x001C >> 2)
#define DP_TRANSMITTER_ENABLE               (0x0080 >> 2)
#define DP_MAIN_STREAM_ENABLE               (0x0084 >> 2)
#define DP_FORCE_SCRAMBLER_RESET            (0x00C0 >> 2)
#define DP_VERSION_REGISTER                 (0x00F8 >> 2)
#define DP_CORE_ID                          (0x00FC >> 2)

#define DP_AUX_COMMAND_REGISTER             (0x0100 >> 2)
#define AUX_ADDR_ONLY_MASK                  (0x1000)
#define AUX_COMMAND_MASK                    (0x0F00)
#define AUX_COMMAND_SHIFT                   (8)
#define AUX_COMMAND_NBYTES                  (0x000F)

#define DP_AUX_WRITE_FIFO                   (0x0104 >> 2)
#define DP_AUX_ADDRESS                      (0x0108 >> 2)
#define DP_AUX_CLOCK_DIVIDER                (0x010C >> 2)
#define DP_TX_USER_FIFO_OVERFLOW            (0x0110 >> 2)
#define DP_INTERRUPT_SIGNAL_STATE           (0x0130 >> 2)
#define DP_AUX_REPLY_DATA                   (0x0134 >> 2)
#define DP_AUX_REPLY_CODE                   (0x0138 >> 2)
#define DP_AUX_REPLY_COUNT                  (0x013C >> 2)
#define DP_REPLY_DATA_COUNT                 (0x0148 >> 2)
#define DP_REPLY_STATUS                     (0x014C >> 2)
#define DP_HPD_DURATION                     (0x0150 >> 2)
#define DP_MAIN_STREAM_HTOTAL               (0x0180 >> 2)
#define DP_MAIN_STREAM_VTOTAL               (0x0184 >> 2)
#define DP_MAIN_STREAM_POLARITY             (0x0188 >> 2)
#define DP_MAIN_STREAM_HSWIDTH              (0x018C >> 2)
#define DP_MAIN_STREAM_VSWIDTH              (0x0190 >> 2)
#define DP_MAIN_STREAM_HRES                 (0x0194 >> 2)
#define DP_MAIN_STREAM_VRES                 (0x0198 >> 2)
#define DP_MAIN_STREAM_HSTART               (0x019C >> 2)
#define DP_MAIN_STREAM_VSTART               (0x01A0 >> 2)
#define DP_MAIN_STREAM_MISC0                (0x01A4 >> 2)
#define DP_MAIN_STREAM_MISC1                (0x01A8 >> 2)
#define DP_MAIN_STREAM_M_VID                (0x01AC >> 2)
#define DP_MSA_TRANSFER_UNIT_SIZE           (0x01B0 >> 2)
#define DP_MAIN_STREAM_N_VID                (0x01B4 >> 2)
#define DP_USER_DATA_COUNT_PER_LANE         (0x01BC >> 2)
#define DP_MIN_BYTES_PER_TU                 (0x01C4 >> 2)
#define DP_FRAC_BYTES_PER_TU                (0x01C8 >> 2)
#define DP_INIT_WAIT                        (0x01CC >> 2)
#define DP_PHY_RESET                        (0x0200 >> 2)
#define DP_PHY_VOLTAGE_DIFF_LANE_0          (0x0220 >> 2)
#define DP_PHY_VOLTAGE_DIFF_LANE_1          (0x0224 >> 2)
#define DP_TRANSMIT_PRBS7                   (0x0230 >> 2)
#define DP_PHY_CLOCK_SELECT                 (0x0234 >> 2)
#define DP_TX_PHY_POWER_DOWN                (0x0238 >> 2)
#define DP_PHY_PRECURSOR_LANE_0             (0x023C >> 2)
#define DP_PHY_PRECURSOR_LANE_1             (0x0240 >> 2)
#define DP_PHY_POSTCURSOR_LANE_0            (0x024C >> 2)
#define DP_PHY_POSTCURSOR_LANE_1            (0x0250 >> 2)
#define DP_PHY_STATUS                       (0x0280 >> 2)

#define DP_TX_AUDIO_CONTROL                 (0x0300 >> 2)
#define DP_TX_AUD_CTRL                      (1)

#define DP_TX_AUDIO_CHANNELS                (0x0304 >> 2)
#define DP_TX_AUDIO_INFO_DATA(n)            ((0x0308 + 4 * n) >> 2)
#define DP_TX_M_AUD                         (0x0328 >> 2)
#define DP_TX_N_AUD                         (0x032C >> 2)
#define DP_TX_AUDIO_EXT_DATA(n)             ((0x0330 + 4 * n) >> 2)
#define DP_INT_STATUS                       (0x03A0 >> 2)
#define DP_INT_VBLNK_START                  (1 << 13)
#define DP_INT_MASK                         (0x03A4 >> 2)
#define DP_INT_EN                           (0x03A8 >> 2)
#define DP_INT_DS                           (0x03AC >> 2)


//////////////////////////////////////////////////////////////
